Embodiments of the present invention relate to processor-based systems, and more particularly to such systems including multiple components in communication with each other.
Modern computer systems are designed around a processor. Increasing efficiencies in semiconductor processing (e.g., shrinking device sizes in advanced technology nodes) provide opportunities for increasing functionality. Many current systems are configured as dual processor (DP) or multiprocessor (MP)-based systems in which two or more processors are present. Typically, such processors may be adapted within processor sockets of a motherboard or other circuit board of a system. Rather than a traditional shared bus topology, advanced platforms are being developed using new protocols for connecting processors and chipset components of a platform. Some of these protocols are implemented using a point-to-point (PTP) interconnect model that provides a high bandwidth. Coherent and scalable interconnects connect components such as processors, hub agents, memory and other system components together.
In addition to inter-processor communications which may be according to a given protocol, such as a PTP interconnect-based protocol, a system may be configured to include or have support for multiple peripheral devices such as input/output (I/O) or other such devices. Oftentimes a given system implementation will include support for N number of I/O slots. Because the industry trend is to integrate I/O capabilities on a processor, one option for providing such I/O capability is to include all sufficient pins and corresponding circuitry within a processor to support all N slots via a single processor. However, such an implementation is not cost effective and is further wasteful of chip area, as typically DP and MP systems are configured with more than one processor in the system. For example, if a MP system includes M processors, support for only N/M number of I/O slots would need to be present in each processor. However, at the same time there can be some configurations of DP or MP systems in which not all M processors are present.